Conductively doped silicon regions are conventionally utilized as source/drain regions of field effect transistors and as other node locations in integrated circuitry. In fabricating integrated circuitry having such regions, insulative layers are typically fabricated over the regions and contact openings are formed therethrough to the regions. Conductive material is ultimately received within the openings and makes electrical connection with the conductively doped source/drain or other regions. Exemplary conductive materials include conductively doped polysilicon and other semiconductive materials, metals, and metal compounds.
Refractory metal silicides, such as titanium silicide, have been utilized as part of the conductive material, typically as an interface region between the conductively doped silicon region and other overlying conductive material. One prior art method of forming the titanium silicide is to deposit elemental titanium and thereafter heat the substrate to cause a reaction of the deposited titanium with underlying silicon to form the silicide. Alternately, deposition conditions can be selected such that the depositing titanium reacts with the silicon from the substrate during deposition to form the silicide. In either instance, silicon is consumed from the underlying substrate diffusion junction region in forming the silicide.
In certain applications, particularly in light of the ever-increasing density of circuitry being fabricated, it is highly undesirable for a significant quantity of the underlying silicon of the junction to be consumed. Accordingly, methods have been developed which prevent, or at least reduce, underlying silicon consumption by providing a silicon source other than or in addition to the silicon of the substrate for forming the silicide. One prior art method is to plasma enhance, chemically vapor deposit the silicide by combining a silane gas and TiCl4 under suitable reaction conditions to form titanium silicide which deposits over the junction region with minimal if any consumption of substrate silicon. Unfortunately, the wafer surface has been found on occasion to become contaminated with particles in processes utilizing TiCl4 and a silane as compared to primarily forming the silicide by reacting titanium with silicon of the substrate.
It was surmised that the particles which were undesirably forming on the wafers might be occurring during either or both of the actual titanium silicide deposition or after the deposition when the wafers were being moved into and out of the reactor chamber. While unclear, it was theorized that the particle formation might be occurring from silane and/or chlorine constituents adhering to the chamber sidewalls perhaps as a result of the deposition, or that chlorine was somehow undesirably being added to the chamber walls during a chamber cleaning which uses chlorine intermediate each wafer deposition.
For example, one exemplary prior art processing intending to reduce particle count employs a Cl2 clean between titanium suicide depositions on separate wafers. For example, after a silicide deposition on one wafer within a reactor chamber, the wafer is removed from the chamber. Then, an argon flow of 500 sccm as a purge gas is flowed through the chamber. This is followed by a Cl2 flow of 2,000 sccm for two seconds as a stabilizing step, with the Cl2 flow then being continued at 2,000 sccm for an additional 15 seconds. The intended effect of the Cl2 clean is to remove titanium material which might undesirably adhere to the internal surfaces of the chamber during the titanium silicide deposition. Upon completion of the Cl2 cleaning step, an 8,000 sccm argon purge feeding is conducted to remove the chlorine. This is followed by a flow of Ar at 8,000 sccm in combination with 1,000 sccm of He. He is lighter than Ar, and can facilitate chamber purging and cleaning, and also facilitates temperature control within the chamber. Subsequently, another wafer is provided within the chamber, and titanium silicide deposition is conducted.
The above-described cleaning process is typically conducted between each single wafer deposition, and typically in the absence of plasma. Yet every 10 to 20 wafer depositions, the chamber is also typically subjected to a plasma clean with Cl2 to better clean/remove titanium from the chamber walls. Further, every 5,000 or so wafer depositions, the whole system is subjected to an atmospheric/room ambient pressure wet clean and scrub (i.e., using NH4OH, H2O2 and isopropyl alcohol in various steps) whereby the whole system is cleaned out. The other above-described cleanings are typically conducted with the reactor chamber essentially at the deposition pressure and temperature conditions.
The invention was principally motivated towards overcoming the above-described surface defect issues, but is in no way so limited. The invention is only limited by the accompanying claims as literally worded without limiting or interpretative reference to the specification, and in accordance with the doctrine of equivalents.